1. Field of the Invention
The present invention relates to a master slice type integrated circuit system and particularly to such an integrated circuit system which can set the channel width of a transistor at the optimum level in a Large Scale Integration LSI chip for every block area thereof to optimize the speed, power consumption, integration and other factors depending on the circuit function. The present invention also concerns a method of making such an integrated circuit system.
2. Description of the Prior Art
A gate array, which is one form of the master slice type integrated circuit systems, comprises basic cells 2 disposed on the central area 1a of a chip 1 in the form of a matrix and input/output cells 5 disposed on the peripheral area 1b of the chip 1 in the form of a ring surrounding the basic cell matrix, as shown in FIG. 2.
Each of the basic cells 2 comprises a plurality of active elements. A plurality of such basic cells 2 are connected together by wiring to form a function cell having a logical function.
The input/output cells 5 disposed on the peripheral area 1b of the chip 1 also connected together by wiring to form an input/output function cell having a logical function. An area 4 between the central and peripheral areas 1a, 1b of the chip 1 serves as an exclusive wiring area for connecting the input/output cells 5 to the internal function cells.
In such a conventional sea-of-gate type gate array as shown in FIG. 2, the basic cells 2 have the same configuration throughout the chip, including the same channel widths Wp and Wn of the P- and N-channel type MOS transistors which define the basic cells 2.
For such a reason, the prior art is limited in that even if function blocks such as RAM, ROM and other blocks are to be formed, they must necessarily be composed of the basic cells of the same configuration. If a RAM is to be made, the area of a memory cell per one bit will be over ten times larger than that of the custom design. Since such a memory cell has its unnecessarily large capacitance, the entire LSI will have an increased power consumption. The formation of a large-capacity RAM in the sea-of-gate type gate array of the prior art is of almost no practical use in the viewpoint of economy such as integration, power consumption and others.
As a result of that the circuits have been increased in the scale, the efficiency of the gate array pursuing only higher wiring rate and speed is extremely inferior to that of an optimized custom chip which is designed to minimize a so-called speed/consumption impulse and to maximize the integration even if they have the same logical function.
It may be believed that this results from the highest priority of reduction of the time for delivery for producing many kinds of gate arrays with small production at the sacrifice of speed, power consumption and integration which should be primarily pursued in LSI.
On the other hand, it is said that in developing such system-on-silicon LSI, the number of gates for practically disposing function cells by such an automatic placement and routing as in the gate array without consideration of the floor plan is limited to twenty or thirty thousands.
It is thus predicted that such a large-scaled circuit as will be developed is in the form of a chip which includes a plurality of system clocks, bus lines, RAMs, ROMs, ALUs and registers through the entire system and further has various different logic circuits. However, we cannot adopt a full custom design which provides different channel length and width of transistors for every function cell to optimize the speed, integration and power consumption for every function block.
This is because the specification and design of the system will necessarily be changed during development of such a large-scaled circuit. In such a case, the production of LSI must basically be restarted from the first step. This leads to the delayed time for delivery and associated cost which are several times larger than those of a gate array in which the specification thereof can be changed only by changes of the wiring step.
Techniques for forming MOS transistors having different channel widths and transistor sizes in one LSI chip are disclosed in Japanese Patent Application Laid-Open No. 58-51536 and Japanese Patent Application Laid-Open Nos. 3-145762, 2-268464 and 5-48050.
In the technique of Japanese Patent Application Laid-Open No. 58-51536, gate electrodes 402 are formed on the upper layers of N- and P-type diffusion regions 400, 401 to form MOS type transistors, as shown in FIG. 18. The MOS type transistors are different in channel width W from one another in the LSI chip.
According such a technique, however, the patterns of the wiring layers (not shown) formed on the upper layers of the gate electrodes 402 are also variable. When the gate electrode 402 is to be connected to the wiring layer on the upper layer thereof according to the prior art shown in FIG. 18, contacts must be formed on enlarged area portions 402a and 402b formed outside of the N- and P-type diffusion regions 400, 401 at the opposite ends of the gate electrode 402. When the channel widths W are to be increased, the positions of the enlarged area portions 402a, 402b must be placed outside of the N- and P-type diffusion regions 400, 401.
According to the invention of Japanese Patent Application Laid-Open No. 58-51536, therefore, the positions of contacts and the patterns of the wiring layers are variable if it is particularly wanted to increase the channel width W, For such a reason, the wiring step including the design of exposure mask is required to be re-designed.
In the technique of Japanese Patent Application Laid-Open No. 3-145762, two smaller P-type diffusion regions 410 and two smaller N-type diffusion regions 411 are formed with gate electrodes 412 being formed on the upper layers of the respective diffusion regions 410 and 411 to provide first basic cells, as shown in FIG. 19. A common gate electrode 422 is formed on the upper layers of larger N- and P-type diffusion regions 420, 421 to provide a second basic cell as shown in FIG. 20. Thus, two types of MOS transistors having different channel widths are formed.
Also in the invention of Japanese Patent Application Laid-Open No. 3-145762, however, the positions of the enlarged area portions 412a and 422a must similarly be changed if it is wanted to increase the channel widths of FIGS. 19 and 20. The contact positions and wiring patterns must also be changed.
The invention of Japanese Patent Application Laid-Open No. 2-268464 forms a common gate electrode over four diffusion regions 410 and 411 shown in FIG. 19. Basically, this is of the same structure as that of the first basic cell disclosed in the Japanese Patent Application Laid-Open No. 3-145762.
In the usual steps of designing and producing such a LSI, the channel width of the MOS transistor must frequently be changed due to the change of fan-out resulting from the logical simulation. Even if the channel width or transistor size is to be optimized for every design as in the aforementioned three proposals, the change of channel width is necessarily associated with the designing and producing steps. This cannot practically be accomplished if the wiring step is greatly changed.
According to the invention of Japanese Patent Application Laid-Open No. 5-48050, P- and N-type diffusion regions having different channel widths are juxtaposed in one direction. When the contact positions and wiring patterns are changed, a MOS transistor having an appropriate one of the channel widths is formed. This invention greatly reduces the efficiency of gate utilization, since the number of wiring steps corresponding to the number of channel widths is required, and there is always some diffusion regions having unnecessary channel widths.